The semiconductor integrated circuit (IC) industry has experienced rapid growth, Technological advances in IC materials and designs have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs, in the course of integrated circuit revolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs.
As semiconductor device sizes continue to shrink, it has become increasingly difficult to meet device planarization requirements in fabrication. Planarization methods known to the inventors typically involve performing a chemical-mechanical-polishing (CMP) process on a semiconductor wafer. However, these traditional planarization methods have not been able to achieve satisfactory performance for wafers having high topography (more than 5 μm), such as those used in MicroElectroMechanical Systems (MEMS) process technologies, MEMS have multiple deposited films that are as much as 10-20 times thicker in some cases than CMOS counterparts, Large step heights and fissures called “seams” that are often formed between insulating material layers present a challenge to CMP and/or etch hack planarization. During planarization CMP loading resulting from a high topography wafer may cause undesirable “dishing” of the insulating material resulting in a nonplanar surface and the opening up of seams. Consequently, the surface of the wafer may not be flat or planar enough for subsequent fabrication processes. For example, the surface of the wafer may not be able to be patterned because of the limited depth of focus in lenses in optical lithography and the loss of linewidth control during photolithography. Acceptable wafer planarity in wafers having high topography is therefore critical for chip yield and long-term reliability.